机译:具有−243.8 dB FOM的基于5 GHz小数N ADC的数字锁相环
Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan;
Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan;
Phase locked loops; Voltage-controlled oscillators; Standards; Phase noise; Dynamic range; Delays;
机译:基于相位插值器的分数计数器,用于全数字分数N锁相环
机译:具有单端注入技术和ILFD辅助注入定时校准技术的18-23 GHz 57.4fs RMS抖动−253.5-dB FoM次谐波注入锁定全数字PLL
机译:使用数字子采样架构的2.2 GHz -242 dB-FOM 4.2 mW ADC-PLL
机译:一个0.008mm 2 sup> 2.4GHz I型子采样基于环振荡器的锁相环,具有239.7dB FoM和-64dBc参考杂散
机译:数字增强技术,用于数字分数-N锁相环
机译:具有延迟耦合的数字锁相环的自组织同步理论与实验
机译:采用小数N分频pLL设计2.3 GHz频率的锁相环移动WimaX