Reducing Power Dissipation, Delay, and Area in Logic Circuits by Narrowing Transistors

摘要

An important aspect of fast CMOS logic-circuit design is transistor sizing. Designers routinely set transistor channel lengths at the minimal values the process permits (unless there is a need to introduce delay). Specification of channel widths, however, requires careful consideration and is based mainly on the capacitive load the circuit must drive and on considerations of energy dissipation and chip area. Experienced designers use heuristic techniques to help with this aspect of circuit design. Sutherland and his associates have developed a powerful systematic method called logical effort. The method presented in this article, based on an analysis at the logic level, enables designers to identify transistors in certain logic elements whose channels can be narrowed to a minimum without incurring penalties. The logical effort method, or some other procedure, can then follow this preliminary step. Rabaey, Chandrakasan, and Nikolic present a simple situation that employs minimum-width transistors and clearly incurs no penalty. In this example, a weak feedback inverter serves to make a dynamic latch static. This article provides a systematic generalization of this idea. In a CMOS NAND gate, each PMOS transistor connects Z, the gate output, to supply voltage V_(DD). Suppose that with all input signals high, gate input X_(i) is turned off (V_(i) is switched from V_(DD) to 0). This activates PMOS transistor T_(pi), and current flows through its channel to charge output capacitance C_(out). The time constant for this charging process is the product of C_(out) and channel resistance R_(chi). I'll generally make the worst-case assumption that only one PMOS transistor is initially activated to turn on Z. I am also assuming that all transistor channel lengths are fixed at the minimal permissible values. Components of C_(out) include the input capacitance of the device (or devices) driven by the gate, and the gate's intrinsic capacitance, which consists of components from each transistor. Internal and external gate wiring also contribute. Of particular interest here is the contribution to the output capacitance made by each PMOS transistor of the NAND gate. This is roughly proportional to transistor channel width W_(p). Because each transistor's contribution is only a fraction of C_(out), the value of C_(out) increases much less than linearly with W_(p). Channel resistance R_(ch) is inversely proportional to channel width W_(p). Halving W_(p) for transistor T_(pi) will double R_(chi), while C_(out) will decrease by much less than half. Therefore, the time constant for the rise of V_(out) will increase significantly for transitions in which C_(out) is charged by the narrowed transistor when its gate signal switches to 0. But what about output transitions driven by other transistors? V_(out), when driven by a different transistor, T_(pj), will rise with a smaller time constant, because C_(out) decreases when W_(pi) decreases. Now consider a situation in which output voltage V_(z) is supposed to fall because X_(i), the signal feeding transistors T_(pi) and T_(ni), changes from 0 to 1 (assuming the other input signals to the gate are already high). Current flowing to ground through a series connection of activated NMOS transistors discharges C_(out). As before, C_(out) decreases as a result of narrowing T_(pi), which reduces the time constant for the output change. Because the capacitance that the source of the X_(i) signal sees also decreases as a consequence of reducing W_(pi), there is an additional reduction in Z's response time to the signal that increases X_(i). This effect also compensates, to some extent, for the increased delay in Z's response to a decrease in X_(i). In CMOS logic, losses due to the charging and discharging of capacitors strongly dominate power dissipation. To the extent that narrowing channels reduces circuit capacitance, the circuit's energy consumption will also decrease. In summary, a narrower PMOS transistor T_