Collapsing the CMOS transistor chain to an effective single equivalent transistor

摘要

A method for collapsing the transistor chain of CMOS gates to a single equivalent transistor is introduced. The width of the equivalent transistor is calculated taking into account the operating conditions of each transistor in the structure, resulting in very good agreement with SPICE simulations. Second- order effects such as carrier velocity saturation in submicron devices, body effect and coupling capacitance are considered and ramp inputs are used. The actual time point when the chain starts conducting which influences significantly the accuracy of the model is also extracted. Finally, an algorithm to collapse every possible input pattern to a single input is introduced.