首页> 外国专利> Low-Vt CMOS transistor design using a single mask and without any additional implants by way of tailoring the effective channel length (Leff)

Low-Vt CMOS transistor design using a single mask and without any additional implants by way of tailoring the effective channel length (Leff)

机译:通过定制有效沟道长度(Leff),使用单个掩模且无需任何额外注入的低电压CMOS晶体管设计

摘要

Low threshold voltage transistors are fabricated by removing oxide spacers from the poly gate sidewalls of the transistors that are to be low threshold voltage. This causes the effective channel length of the low Vt transistors to be shorter than that of the core transistors, which causes lower threshold voltage.
机译:通过从要成为低阈值电压的晶体管的多晶硅栅极侧壁去除氧化物间隔物来制造低阈值电压晶体管。这导致低Vt晶体管的有效沟道长度比核心晶体管的有效沟道长度短,这导致较低的阈值电压。

著录项

  • 公开/公告号US2002086484A1

    专利类型

  • 公开/公告日2002-07-04

    原文格式PDF

  • 申请/专利权人 MEHROTRA MANOJ;

    申请/专利号US20010007030

  • 发明设计人 MANOJ MEHROTRA;

    申请日2001-11-08

  • 分类号H01L21/336;H01L21/8234;H01L21/8236;H01L29/76;H01L29/94;H01L31/062;H01L31/113;

  • 国家 US

  • 入库时间 2022-08-22 00:49:55

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