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Bacterial foraging driven exploration of multi cycle fault tolerant datapath based on power-performance tradeoff in high level synthesis

机译:基于功率-性能折衷的高级综合细菌搜寻驱动的多周期容错数据路径探索

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摘要

Technology evolution and energy of particle impact both plays a major role in inducing multi-cycle transient fault (longer duration transient) in a device. However, designing an optimized multi-cycle fault tolerant system is non-trivial. This paper presents a novel design space exploration (DSE) approach for multi-cycle transient fault tolerant datapath based on user power-delay constraints during high level synthesis (HIS). To the best of the authors' belief, this is the first work to solve this problem in the literature so far. More specifically, the current work in the literature so far utilizes 'triple modular redundancy (TMR)' to design a fault tolerant datapath, however, this paper proposes a 'dual modular redundancy (DMR) design with equivalent circuit' scheme to achieve the same. The novel equivalent circuit that works with DMR systems performs the function of extracting the correct output from the DMR design. Further, the proposed work is the first work in the literature that handles multi-cycle transient faults during design space exploration of fault tolerant datapath. Therefore, key contributions of this paper are as follows: (a) novel multi-cycle transient fault tolerant algorithm that has capability to isolate original and duplicate units in a DMR with respect to the transient fau (b) novel DSE approach that combines our fault tolerant algorithm along with user specified conflicting power-performance constraint that guides this intractable search problem to reach an high quality fault tolerant solution without violating the power budget and delay requirement; (c) integrates a heuristic based on bacterial foraging optimization algorithm (BFOA) that performs adaptive searching. Finally, results indicated an average improvement in Quality of Results (QoR) of >24% and reduction in hardware usage of >57% of the final solution compared to similar approach. (C) 2015 Elsevier Ltd. All rights reserved.
机译:技术的发展和粒子撞击的能量都在引起设备中的多周期瞬态故障(较长持续时间的瞬态)中起着重要作用。但是,设计优化的多周期容错系统并非易事。本文提出了一种新的设计空间探索(DSE)方法,该方法用于在高级综合(HIS)期间基于用户功率延迟约束的多周期瞬态容错数据路径。尽作者所能相信,这是迄今为止解决文献中这一问题的第一篇著作。更具体地说,到目前为止,目前文献中的工作都是利用“三重模块冗余(TMR)”设计容错数据路径,但是,本文提出了“具有等效电路的双模块冗余(DMR)设计”方案来实现相同的目的。 。与DMR系统配合使用的新型等效电路具有从DMR设计中提取正确输出的功能。此外,所提出的工作是文献中在容错数据路径的设计空间探索期间处理多周期瞬态故障的第一项工作。因此,本文的主要贡献如下:(a)新颖的多周期瞬态容错算法,能够针对瞬态故障隔离DMR中的原始单元和重复单元; (b)新颖的DSE方法,将我们的容错算法与用户指定的有冲突的电源性能约束相结合,可以指导这一棘手的搜索问题,从而在不违反电源预算和延迟要求的情况下达到高质量的容错解决方案; (c)集成了基于细菌觅食优化算法(BFOA)的启发式算法,该算法执行自适应搜索。最后,结果表明,与类似方法相比,最终解决方案的结果质量(QoR)平均提高了24%以上,硬件使用量降低了57%以上。 (C)2015 Elsevier Ltd.保留所有权利。

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  • 来源
    《Expert Systems with Application》 |2015年第10期|4719-4732|共14页
  • 作者单位

    Indian Inst Technol, Comp Sci & Engn, Indore 452020, Madhya Pradesh, India;

    Indian Inst Technol, Comp Sci & Engn, Indore 452020, Madhya Pradesh, India;

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