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首页> 外文期刊>IEEE Transactions on Components, Hybrids, and Manufacturing Technology >Resistive signal line wiring net designs in multichip modules
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Resistive signal line wiring net designs in multichip modules

机译:多芯片模块中的电阻信号线接线网设计

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摘要

To approximate the frequency dependence of the characteristic impedance and signal attenuation of a DC resistive transmission line, formulas with one pole and one zero on the negative real axis are proposed. The algebraic time-domain solutions for the near-end and far-end voltages of this line, which is driven by a constant resistance source, are derived. The far end of this line is either open-circuited or terminated by a constant resistance load. Nomographs to guide the multichip module (MCM) wiring net designs are developed and presented. Their application is illustrated by an MCM-D address bus wiring net design example.
机译:为了近似直流电阻传输线的特征阻抗与信号衰减的频率相关性,提出了在负实轴上具有一极零一的公式。推导了由恒定电阻源驱动的该线路近端和远端电压的代数时域解。该线的远端开路或被恒定电阻负载端接。开发并展示了指导多芯片模块(MCM)布线网络设计的线描仪。 MCM-D地址总线布线网络设计示例说明了它们的应用。

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