A 1 TB/s 1 pJ/b 6.4 ${rm mm}^{2}/{rm TB/s}$ QDR Inductive-Coupling Interface Between 65-nm CMOS Logic and Emulated 100-nm DRAM

摘要

1 TB/s 1 pJ/b 6.4 ${rm mm}^{2}/{rm TB/s}$ inductive-coupling interface between 65-nm complementary metal–oxide–semiconductor (CMOS) logic and emulated 100-nm dynamic random access memory (DRAM) is developed. ${rm BER}<10^{-16}$ operation is examined in 1024-bit parallel links. Compared to the latest wired 40-nm DRAM interface, the bandwidth is increased to 32$times$ , and the energy consumption and the layout area are reduced to 1/8 and 1/22, respectively.