DRAM MEMORY PHYSICAL LAYER INTERFACE LOGIC FOR GENERATING DYNAMIC RANDOM ACCESS MEMORY DRAM COMMANDS WITH PROGRAMMABLE DELAYS

摘要

Multiple registers 222 implemented in association with memory physical layer interface (PHY) 140, 205 may include one or more instruction words 300 indicating one or more instructions and one or more delays 415, 515, 535, 540. Can be used to store The training engine 220 implemented in the memory PHY may generate a fast programmable sequence of instructions 410, 420, 430, 510, 520, 525 for delivery to the external memory 210, based on one or more delays. You can delay the command. A fast programmable sequence of instructions can be generated based on one or more instruction words.