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Memory physical layer interface logic for generating dynamic random access memory (DRAM) commands with programmable delays
Memory physical layer interface logic for generating dynamic random access memory (DRAM) commands with programmable delays
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机译:存储器物理层接口逻辑,用于生成具有可编程延迟的动态随机存取存储器(DRAM)命令
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摘要
A plurality of registers implemented in association with a memory physical layer interface (PHY) can be used to store one or more instruction words that indicate one or more commands and one or more delays. A training engine implemented in the memory PHY can generate at-speed programmable sequences of commands for delivery to an external memory and to delay the commands based on the one or more delays. The at-speed programmable sequences of commands can be generated based on the one or more instruction words.
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