Thermo-structural model of stacked field-programmable gate arrays with through-silicon vias

摘要

A new 3-D full-scale thermo-structural finite element model of two-stack field-programmable gate arrays (FPGAs) with through-silicon vias (TSVs), which is developed from an experimentally validated single-stack FPGA model, is proposed. Typical 3-D distributions and evolutions of temperature and von Mises stress on both the active layers and TSVs arc presented.