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首页> 外文期刊>International journal of information technology project management >Building Information Modeling using Hardware Genetic Algorithms with Field-Programmable Gate Arrays
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Building Information Modeling using Hardware Genetic Algorithms with Field-Programmable Gate Arrays

机译:使用带有现场可编程门阵列的硬件遗传算法进行建筑信息建模

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摘要

Genetic algorithms (GAs) have found many applications in various fields such as physics, signal processing, artificial intelligence and recently construction engineering management. For a long time, GAs are usually criticized to be time-consuming, making it unpractical for real-time applications. This paper presents a new technique which can be used: (1) to automate construction activities, and (2) to improve building information modeling which has become an attractive research topic around the world. Different from the generic GA techniques employed in the literature, this paper proposes a new GA using hardware with field-programmable gate arrays. The proposed technique is shown to improve speed and lessen computational power. Hardware implementation of GA using static random access memory-based field-programmable gate arrays with synthesizable very hardware description language coding is introduced. Detailed analyses on the field-programmable gate arrays are given which show that it is suitable for real-time applications. As a result, GA is modified so that it can be implemented in series and parallel which can greatly improve computational hardware performance. Configuration of parallelization is available with a peripheral component interconnect interface, which further helps to form a fast optimization tool for real-time applications. The ultimate goal of this paper is thus to design an effective GA technique which can be employed to support building information modeling and to effectively automate critical processes in construction projects.
机译:遗传算法(GA)已在物理,信号处理,人工智能以及最近的建筑工程管理等各个领域中找到了许多应用。很长一段时间以来,GA通常被批评为耗时的,使其不适用于实时应用。本文提出了一种可以使用的新技术:(1)使建筑活动自动化,以及(2)改善建筑信息模型,这已成为世界范围内一个有吸引力的研究主题。与文献中采用的通用GA技术不同,本文提出了一种使用具有现场可编程门阵列的硬件的新型GA。所提出的技术表明可以提高速度并减少计算能力。介绍了使用基于静态随机存取存储器的现场可编程门阵列和可综合的非常硬件描述语言编码的遗传算法的硬件实现。给出了对现场可编程门阵列的详细分析,表明该阵列适用于实时应用。结果,对GA进行了修改,使其可以串行和并行实现,从而可以大大提高计算硬件性能。并行配置可通过外围组件互连接口使用,这进一步有助于形成用于实时应用的快速优化工具。因此,本文的最终目标是设计一种有效的GA技术,该技术可用于支持建筑信息建模并有效地自动化建筑项目中的关键过程。

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