10 Gbit/s serial link receiver with speculative decision feedback equaliser using mixed-signal adaption in 65 nm CMOS technology

摘要

A 10 Gbit/s serial link receiver with an offset-calibrated continuous-time linear equaliser, an adaptive one-tap half-rate speculative decision feedback equaliser (DFE) and a phase-interpolator-based clock and data recovery is presented. Adaption of the DFE is achieved by using a novel mixed-signal implementation of the sign-sign least mean square algorithm to save the cost of hardware and power. Fabricated in 65 nm CMOS technology, the receiver can totally compensate 24.85 dB channel loss at a bit error rate of 10. The active chip area is 0.08 mm and the total power consumption is 57 mW from a 1.2 V supply.