Design Techniques for a Mixed-Signal I/Q 32-Coefficient Rx-Feedforward Equalizer, 100-Coefficient Decision Feedback Equalizer in an 8 Gb/s 60 GHz 65 nm LP CMOS Receiver

摘要

This paper describes a mixed-signal I/Q 32-coefficient receive-side feedforward equalizer (RX-FFE) and 100-coefficient decision feedback equalizer (DFE) for a 60 GHz baseband. Integrated in 65 nm LP CMOS with variable gain amplifiers (VGA), analog phase rotator (PR), and clock generation and phase adjustment circuits, the I/Q equalizer supports 60 GHz WiGig non-line-of-sight (NLOS) channels with > 12 ns of delay spread while consuming 66 mW from a 1.2 V supply at 8 Gb/s. Energy-efficient equalization is achieved by the RX-FFE using a proposed switching matrix architecture, and by implementing the multi-coefficient FFE-DFE summing with cascoded current integration.