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Two-Dimensional Heterojunction Interlayer Tunneling Field Effect Transistors (Thin-TFETs)

机译:二维异质结层间隧穿场效应晶体管(Thin-TFET)

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摘要

Layered 2-D crystals embrace unique features of atomically thin bodies, dangling bond free interfaces, and step-like 2-D density of states. To exploit these features for the design of a steep slope transistor, we propose a Two-dimensional heterojunction interlayer tunneling field effect transistor (Thin-TFET), where a steep subthreshold swing (SS) of mV/dec and a high on-current of A/m are estimated theoretically. The SS is ultimately limited by the density of states broadening at the band edges and the on-current density is estimated based on the interlayer charge transfer time measured in recent experimental studies. To minimize supply voltage while simultaneously maximizing on currents, Thin-TFETs are best realized in heterostructures with near broken gap energy band alignment. Using the WSe/SnSe stacked-monolayer heterostructure, a model material system with desired properties for Thin-TFETs, the performance of both -type and -type Thin-TFETs is theoretically evaluated. Nonideal effects such as a nonuniform van der Waals gap thickness between the two 2-D semiconductors and finite total access resistance are also studied. Finally, we present a benchmark study for digital applications, showing the Thin-TFETs may outperform CMOS and III–V TFETs in term of both switching speed and energy consumption at low-supply voltages.
机译:层状二维晶体具有原子薄体的独特特征,悬空的无键界面以及阶梯状的二维状态密度。为了利用这些特性设计陡峭的晶体管,我们提出了一种二维异质结层间隧穿场效应晶体管(Thin-TFET),其中,陡峭的亚阈值摆幅(SS)为mV / dec,高导通电流为A / m是理论上估计的。 SS最终受限于在带边缘变宽的状态密度,并且基于最近的实验研究中测得的层间电荷转移时间来估算导通电流密度。为了使电源电压最小化,同时又使电流最大化,最好在间隙能带对准接近断开的异质结构中实现Thin-TFET。使用WSe / SnSe堆叠单层异质结构(一种具有Thin-TFET所需性能的模型材料系统),从理论上评估了类型和类型的Thin-TFET的性能。还研究了非理想效应,例如两个二维半导体之间的不均匀范德华间隙厚度以及有限的总访问电阻。最后,我们提出了针对数字应用的基准研究,显示出在低电源电压下的开关速度和能耗方面,Thin-TFET可能胜过CMOS和III–V TFET。

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