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FinFET design considerations based on 3-D simulation and analytical modeling

机译:基于3-D仿真和分析建模的FinFET设计注意事项

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Design considerations of the FinFET have been investigated by three-dimensional (3-D) simulation and analytical modeling in this paper. Short-channel effects (SCE) of the FinFET can be reasonably controlled by reducing either silicon fin height or fin thickness. Analytical solution of 3-D Laplace's equation is employed to establish the design equations for the subthreshold behavior in the fully depleted silicon fins. Based on the 3-D analytical electrostatic potential in the subthreshold region, the threshold voltage (V/sub th/) roll-off and the subthreshold swing (S) are estimated by considering the source barrier changes in the most leaky channel path. V/sub th/ roll-off is an exponential function of the ratio of effective channel length to drain potential decay length, which can then be expressed as a function of the fin thickness, the fin height and the gate oxide thickness. The drain-potential decay lengths of single-gate fully depleted SOI MOSFET (FDFET), double-gate MOSFET (DGFET), rectangular surrounding-gate MOSFET (SGFET), and FinFET are compared. The drain potential scaling length and V/sub th/ roll-off can be included into a universal relation for convenient comparison.
机译:本文通过三维(3-D)仿真和分析建模研究了FinFET的设计考虑因素。通过减小硅鳍高度或鳍厚度,可以合理地控制FinFET的短沟道效应(SCE)。利用3-D Laplace方程的解析解建立了完全耗尽的硅鳍中亚阈值行为的设计方程。基于亚阈值区域中的3-D分析静电势,通过考虑最泄漏通道路径中的源极势垒变化来估算阈值电压(V / sub th /)滚降和亚阈值摆幅(S)。 V / sub /滚降是有效沟道长度与漏极电势衰减长度之比的指数函数,然后可以表示为鳍片厚度,鳍片高度和栅极氧化物厚度的函数。比较了单栅完全耗尽的SOI MOSFET(FDFET),双栅MOSFET(DGFET),矩形围栅MOSFET(SGFET)和FinFET的漏极电位衰减长度。漏极电势标定长度和V / sub th /滚降可包含在通用关系中,以方便比较。

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