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A Program for Device Model Parameter Extraction from Gate Capacitance and Current of Ultrathin SiO{sub}2 and High-κ Gate Stacks

机译:从超薄SiO {sub} 2和高κ栅极堆叠的栅极电容和电流中提取器件模型参数的程序

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A modeling tool is demonstrated for fast and automatic gate dielectric characterization and parameter extraction for the 45-nm CMOS technology node and beyond. The model incorporates a nonlinear least squares fitting program with the ability to extract nanometer-scale equivalent oxide thicknesses (EOTs) SiO{sub}2 and high-dielectric-constant (high-κ) gate dielectrics from experimental gate capacitance (C{sub}g-V{sub}g) and gate leakage current (I{sub}g-V{sub}g) with high accuracy and efficiency. A modified Levenberg-Marquardt algorithm was used as the optimization approach. Improvements were made to reduce the chances of becoming stuck in local minima. A previously reported computationally efficient and accurate physically based compact model of self-consistent C{sub}g-V{sub}g and I{sub}g-V{sub}g model for both ultrathin SiO{sub}2 and high-κ gate stacks of EOT down to ~0.5 nm is used as the basis for translating experimental C{sub}g-V{sub}g and I{sub}g)-V{sub}g) data to material and device parameters. In just a few seconds, for single and double layer gate dielectrics, device parameters such as EOTs, surface substrate doping concentrations, flatband voltages, and polysilicon doping concentrations (if applicable) can be extracted from measured gate capacitance data, and parameters such as physical thickness, band offsets, dielectric constants, and tunneling masses for the gate dielectrics can be extracted from measured gate current data. It was found that significant correlation exists between the effects of certain combinations of model parameters, especially for gate tunneling current. Thus, in this program, parameters can be fixed selectively for those already obtained with high confidence from other measurements. Box constraints can also be imposed, at the price of somewhat longer extraction time (up to ~1-7 min), for parameters to be optimized to improve the possibility of finding the correct parameters.
机译:演示了一种建模工具,可用于45nm CMOS技术节点及以后的节点进行快速,自动的栅极介电特性分析和参数提取。该模型包含一个非线性最小二乘拟合程序,该程序能够从实验栅极电容(C {sub}中提取纳米级等效氧化物厚度(EOT)SiO {sub} 2和高介电常数(high-κ)栅极电介质gV {sub} g)和栅极泄漏电流(I {sub} gV {sub} g)具有很高的精度和效率。改进的Levenberg-Marquardt算法被用作优化方法。进行了改进以减少陷入局部最小值的可能性。先前报道的超薄SiO {sub} 2和高κ栅极堆叠的自洽C {sub} gV {sub} g和I {sub} gV {sub} g模型的计算有效且基于物理的紧凑模型EOT低至约0.5 nm用作将实验C {sub} gV {sub} g和I {sub} g)-V {sub} g)数据转换为材料和器件参数的基础。在短短几秒钟内,对于单层和双层栅极电介质,可以从测得的栅极电容数据中提取器件参数,例如EOT,表面衬底掺杂浓度,平带电压和多晶硅掺杂浓度(如果适用),以及物理参数。可以从测得的栅极电流数据中提取出栅极电介质的厚度,带隙,介电常数和隧穿质量。发现在模型参数的某些组合的影响之间存在显着的相关性,特别是对于栅极隧穿电流。因此,在该程序中,对于已经从其他测量中以高置信度获得的参数,可以有选择地固定参数。为了优化参数以提高找到正确参数的可能性,还可能以较长的提取时间(最多约1-7分钟)为代价来施加框约束。

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