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首页> 外文期刊>Electron Devices, IEEE Transactions on >Performance Enhancements in Scaled Strained-SiGe pMOSFETs With $ hbox{HfSiO}_{x}/hbox{TiSiN}$ Gate Stacks
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Performance Enhancements in Scaled Strained-SiGe pMOSFETs With $ hbox{HfSiO}_{x}/hbox{TiSiN}$ Gate Stacks

机译:具有$ hbox {HfSiO} _ {x} / hbox {TiSiN} $栅堆叠的按比例缩放的SiGe pMOSFET的性能增强

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The short-channel performance of compressively strained Si0.77Ge0.23 pMOSFETs with HfSiOx/TiSiN gate stacks has been characterized alongside that of unstrained-Si pMOSFETs. Strained-SiGe devices exhibit 80% mobility enhancement compared with Si control devices at an effective vertical field of 1 MV middotcm-1. For the first time, the on-state drain-current enhancement of intrinsic strained-SiGe devices is shown to be approximately constant with scaling. Intrinsic strained-SiGe devices with 100-nm gate lengths exhibit 75% enhancement in maximum transconductance compared with Si control devices, using only ~20% Ge (~0.8% strain). The origin of the loss in performance enhancement commonly observed in strained-SiGe devices at short gate lengths is examined and found to be dominated by reduced boron diffusivity and increased parasitic series resistance in compressively strained SiGe devices compared with silicon control devices. The effective channel length was extracted from I- V measurements and was found to be 40% smaller in 100-nm silicon control devices than in SiGe devices having the same lithographic gate lengths, which is in good agreement with the metallurgical channel length predicted by TCAD process simulations. Self-heating due to the low thermal conductivity of SiGe is shown to have a negligible effect on the scaled-device performance. These findings demonstrate that the significant on-state performance gains of strained-SiGe pMOSFETs compared with bulk Si devices observed at long channel lengths are also obtainable in scaled devices if dopant diffusion, silicidation, and contact modules can be optimized for SiGe.
机译:具有HfSiOx / TiSiN栅极叠层的压缩应变Si0.77Ge0.23 pMOSFET的短通道性能与非应变Si pMOSFET的短通道性能相同。在1 MV middotcm-1的有效垂直场上,应变SiGe器件与Si控制器件相比,迁移率提高了80%。首次显示本征应变SiGe器件的导通状态漏极电流增强随定标近似恒定。与仅使用约20%Ge(约0.8%应变)的Si控制器件相比,具有100 nm栅极长度的本征应变SiGe器件的最大跨导提高了75%。与在硅控制器件相比,在压缩应变的SiGe器件中,通常观察到应变SiGe器件在短栅极长度时通常观察到的性能增强损失的起因,主要是由于硼扩散率降低和寄生串联电阻增加所致。从I-V测量中提取出有效沟道长度,发现在100 nm硅控制器件中,有效沟道长度比具有相同光刻栅极长度的SiGe器件小40%,这与TCAD预测的冶金沟道长度非常吻合过程模拟。由于SiGe的低导热性,自热对定标器件性能的影响可忽略不计。这些发现表明,如果可以针对SiGe优化掺杂剂扩散,硅化和接触模块,则在定标器件中,与在长沟道长度处观察到的块状Si器件相比,应变SiGe pMOSFET的导通状态性能显着提高。

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