Field-Based Capacitance Modeling for Sub-65-nm On-Chip Interconnect

摘要

Back-end-of-the-line (BEOL) interconnect becomes a limiting factor to circuit performance in scaled complementary metal–oxide–semiconductor design. To accurately extract its paratactic capacitance for circuit simulation, compact models should be scalable with wire geometries and should capture the latest technology advances, such as the air gap and Cu diffusion barrier. This paper achieves these goals based on the distribution of the electric field in on-chip BEOL structures. By decomposing the electric field into various regions, the proposed method physically solves each basic capacitance component into a closed-form solution; the total ground and coupling capacitances are then the sum of all related components. Such a component-based approach is convenient in incorporating new interconnect structures. Its physics basis minimizes the complexity and the error in a traditional model fitting process. Compared with Raphael simulations at the 45-nm node, the new compact model accurately predicts the capacitance value, even in the presence of the air gap and diffusion barrier, covering a wide range of BEOL dimensions. The complete set of equations will be implemented at http://www.eas.asu.edu/~ptm.