Accurate Calculation of Gate Tunneling Current in Double-Gate and Single-Gate SOI MOSFETs Through Gate Dielectric Stacks

摘要

Recently, a new generation of MOSFETs, called multigate transistors, has emerged with geometries that will allow the downscaling and continuing enhancement of computer performance into next decade. The low dimensions in these nanoscale transistors exhibit increasing quantum effects, which are no longer negligible. Gate tunneling current is one of such effects that should be efficiently modeled. In this paper, an accurate description of tunneling in ultrathin body double-gate and single-gate MOSFET devices through layers of high- $kappa$ dielectrics, which relies on the precise determination of quasi-bound states, is developed. For this purpose, the perfectly matched layer method is embedded in each iteration of a 1-D Schrödinger–Poisson solver by introducing a complex stretched coordinate which allows applying artificial absorbing layers in the boundaries.