Shot-Noise-Induced Failure in Nanoscale Flip-Flops Part II: Failure Rates in 10-nm Ultimate CMOS

摘要

In part I of this paper, a robust numerical framework based on Markov queueing theory and nonequilibrium Green's functions was presented to model the fluctuations in a CMOS flip-flop, which could potentially give rise to logic upsets. In part II, this framework is used to investigate quantitatively the failure in time for end-of-roadmap CMOS devices at the $L_{G} = hbox{10} hbox{nm}$ length scale as a function of various parameters such as size, temperature, threshold voltage, process-induced threshold variation, and $V_{DD}$. It is shown quantitatively that process-induced variation and/or use of ultralow $V_{DD}$ make the devices extremely vulnerable to noise. Higher temperatures give rise to higher failure rates through increased thermal fluctuations and through reduced $I_{rm on}/I_{rm off}$ ratios, due to an inverse dependence of the subthreshold slope on temperature. The effect of nonlinear voltage-dependent node capacitors are modeled via the use of arbitrary-shaped queues, and the corresponding results are reported.