50-nm Asymmetrically Recessed Metamorphic High-Electron Mobility Transistors With Reduced Source–Drain Spacing: Performance Enhancement and Tradeoffs

摘要

Whereas gate-length reduction has served as the major driving force to enhance the performance of GaAs- and InP-based high-electron mobility transistors (HEMTs) over the past three decades, the limitation of this approach begins to emerge. In this paper, we present a systematic evaluation of the impact of greatly reduced source–drain spacing on the performance of 50-nm asymmetrically recessed metamorphic HEMTs (MHEMTs). Extremely high extrinsic transconductance has been achieved over a wide drain bias range starting from as low as 0.1 V by reducing source–drain spacing to 0.5 $muhbox{m}$ with a self-aligned (SAL) ohmic process. The measured maximum extrinsic transconductance of 3 S/mm is a new record for all HEMT devices on a GaAs substrate and is equal to the best results reported for InP-based HEMTs. With the use of an asymmetric recess, SAL MHEMTs also demonstrate remarkable improvement in other major figures of merit, including off-state breakdown, on-state breakdown, subthreshold characteristics, $I_{rm ON}/I_{rm OFF}$ ratio, and the voltage gain over the other SAL HEMTs reported so far. However, they still, in a few respects, underperform the conventional devices typically with 2- $muhbox{m}$ source–drain spacing. In particular, the on-state breakdown of the SAL devices has been capped at approximately 2 V, even with a very wide asymmetric recess. It appears that the uniqueness of the SAL technology would best fit applications that require low voltage and/or low DC power consumption, which can be fully tapped only when the parasitic capacitance is also properly controlled with, e.g., a high stem gate process.