Device–Circuit Co-design for Beyond 1 GHz 5 V Level Shifter Using DeMOS Transistors

摘要

This paper presents a device–circuit co-design approach to achieve a low swing, high speed 1.2–5 V level shifter (LS) using drain extended MOS (DeMOS) transistors for system on chip applications in advance CMOS technologies. Limiting factors of the high-voltage devices during transients are identified and accordingly it is shown that the maximum operating frequency of traditional LS can be increased by at least a factor of two. It is demonstrated that optimization of key device parameters of the DeMOS transistor enhances the maximum clock frequency to more than 1 GHz while preserving the device breakdown voltage and duty cycle of the level shifted signal.