首页> 外文期刊>Electron Devices, IEEE Transactions on >Limitations of the High–Low src='/images/tex/276.gif' alt='C'> src='/images/tex/356.gif' alt='V'> Technique for MOS Interfaces With Large Time Constant Dispersion
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Limitations of the High–Low src='/images/tex/276.gif' alt='C'> src='/images/tex/356.gif' alt='V'> Technique for MOS Interfaces With Large Time Constant Dispersion

机译:高-低 src =“ / images / tex / 276.gif” alt =“ C”> src =“ / images / tex / 356.gif” alt =“ V”> 用于具有大时间常数色散的MOS接口的技术

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摘要

We discuss the limitations of the high–low $CV$ technique in evaluating the interface trap density $(D_{rm IT})$ in MOS samples with a large time constant dispersion, as occurs in silicon carbide (SiC). We show that the high–low technique can seriously underestimate $D_{rm IT}$ for samples with large time constant dispersion, even if elevated temperatures are used to extend the range of validity.
机译:我们讨论了在评估具有大时间常数分散性的MOS样品中的界面陷阱密度$(D_ {rm IT})$时,高-低$ CV $技术的局限性,这在碳化硅(SiC)中会发生。我们表明,即使使用高温扩展了有效范围,高低技术也可以严重低估具有较大时间常数分散性的样品的D_ {rm IT} $。

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