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Single-Event Burnout Hardening of Power UMOSFETs With Integrated Schottky Diode

机译:集成肖特基二极管的功率UMOSFET的单事件烧断硬化

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This paper presents 2-D numerical simulation results of single-event burnout (SEB) for hardened power U-shaped gate MOSFET (UMOSFET) with Schottky diode (SD-UMOSFET). In this device, a Schottky diode is integrated into every unit cell of power UMOSFETs. We find that the Schottky contact can leak off the generated holes caused by an ion's impact, and the SEB threshold voltage can be improved. The hardened structure means the addition of an N buffer layer based on a power UMOSFET here. So, the 70 V hardened power SD-UMOSFET discussed in this paper contains a Schottky diode and an N buffer layer, which can work normally without affecting steady-state characteristics. The reverse recovery characteristic and SEB performance of hardened SD-UMOSFET are both enhanced effectively. The reverse recovery time decreases 49%, the reverse recovery current peak decreases 56%, and the softness factor increases more than 100% when the hardened SD-UMOSFET is compared with the standard UMOSFET. In addition, the SEB threshold voltage increases to 64 V, which is 91% of the rated breakdown voltage.
机译:本文介绍了具有肖特基二极管(SD-UMOSFET)的硬化功率U形栅极MOSFET(UMOSFET)的单事件烧坏(SEB)的二维数值模拟结果。在该器件中,肖特基二极管集成到功率UMOSFET的每个单位单元中。我们发现,肖特基接触可以泄漏由于离子的撞击而产生的空穴,并且可以提高SEB阈值电压。此处的硬化结构意味着添加基于功率UMOSFET的N缓冲层。因此,本文讨论的70 V硬化功率SD-UMOSFET包含一个肖特基二极管和一个N缓冲层,它们可以正常工作而不会影响稳态特性。硬化的SD-UMOSFET的反向恢复特性和SEB性能均得到有效增强。当将硬化的SD-UMOSFET与标准UMOSFET进行比较时,反向恢复时间减少了49%,反向恢复电流峰值减少了56%,软度系数增加了100%以上。此外,SEB阈值电压增加到64 V,这是额定击穿电压的91%。

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