Ultralow Turn-OFF Loss SOI LIGBT With p-Buried Layer During Inductive Load Switching

摘要

An ultralow turn-OFF loss () silicon-on-insulator lateral insulated-gate bipolar transistor with a p-buried layer (PB SOI LIGBT) is first proposed. A universal model during inductive load turn-OFF is set up, which reveals that low can be achieved by reducing the total integral current charges, reducing the average anode voltage in the first phase and increasing the charge factor . Due to the large capacitance effect and extra hole extraction path induced by the PB, the three ideas for low are demonstrated in the PB SOI LIGBT. Simulation results show that the PB SOI LIGBT can achieve an 85% lower compared with the conventional SOI LIGBT based on 6- SOI layer. Furthermore, the proposed model can be applied to all the IGBTs, and it reveals the mechanism of low of the IGBT with a superjunction structure during inductive load switching.