A Compact Virtual-Source Model for Carbon Nanotube FETs in the Sub-10-nm Regime—Part II: Extrinsic Elements, Performance Assessment, and Design Optimization

摘要

We present a data-calibrated compact model of carbon nanotube (CNT) FETs (CNFETs), including contact resistance, direct source-to-drain, and band-to-band tunneling currents. The model captures the effects of dimensional scaling and performance degradations due to parasitic effects, and is used to study the tradeoffs between the drive current and the leakage current of CNFETs according to the selection of CNT diameter, CNT density, contact length, and gate length for a target contacted gate pitch. We describe a co-optimization study of CNFET device parameters near the limits of scaling with physical insight, and project the CNFET performance at the 5-nm technology node with an estimated contacted gate pitch of 31 nm. Based on the analysis, including parasitic resistance, capacitance, and tunneling leakage current, a CNT density of 180 CNTs/ will enable the CNFET technology to meet the International Technology Roadmap for Semiconductors target of drive current (1.33 mA/), which is within reach of modern experimental capabilities.