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首页> 外文期刊>Solid-State Electronics >High-performance logic transistor DC benchmarking toward 7 nm technology-node between III-V and Si tri-gate n-MOSFETs using virtual-source injection velocity model
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High-performance logic transistor DC benchmarking toward 7 nm technology-node between III-V and Si tri-gate n-MOSFETs using virtual-source injection velocity model

机译:使用虚拟源注入速度模型,将高性能逻辑晶体管DC基准化为III-V和Si三栅极n-MOSFET之间的7 nm技术节点

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摘要

Injection velocity (v(inj)) is a unique figure-of-merit that determines logic transistor ON-current (ION) and switching delay (CV/I). This paper reports on Virtual-Source (VS) based analytical and physical model, which was calibrated by using state-of-the-art experimental data on III-V and Si tri-gate n-MOSFET, aiming to compare High-Performance (HP) logic transistor performance at 7 nm technology-node. We find that a significant increase in the virtual source injection velocity and improvement in the electrostatic integrity are critical, to meet the projected I-ON/I-OFF ratio for the 7 nm technology node. (C) 2015 Published by Elsevier Ltd.
机译:注入速度(v(inj))是确定逻辑晶体管导通电流(ION)和开关延迟(CV / I)的唯一因数。本文报告了基于虚拟源(VS)的分析和物理模型,该模型是通过使用III-V和Si三栅n-MOSFET的最新实验数据进行校准的,旨在比较高性能( HP)逻辑晶体管在7 nm技术节点上的性能。我们发现,为了满足7 nm技术节点的预计I-ON / I-OFF比,虚拟源注入速度的显着提高和静电完整性的提高至关重要。 (C)2015年由Elsevier Ltd.出版

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