Design for Variation-Immunity in Sub-10-nm Stacked-Nanowire FETs to Suppress LER-induced Random Variations

摘要

In order to construct a design that exhibits variation immunity, the impacts of line-edge roughness (LER) of nanowires (NWs) in stacked-nanowire FETs (stacked-NW FETs) are investigated using 3-D LER simulations. To explore the LER-induced performance variations in stacked-NW FETs, three geometrical parameters are considered: 1) the correlation coefficient (P) between the LER profiles of NWs; 2) the cross-sectional area ratio (d) that represents the volume difference between NWs; and 3) the number of stacked NWs (n). In terms of the correlation between the LER profiles of NWs, positively correlated LER profiles cause the largest performance mismatches. In contrast, when the LER profiles between NWs are uncorrelated or negatively correlated, the performance variations are suppressed effectively. On the other hand, the performance variation can be reduced by a volume difference between the NWs in stacked-NW FETs (especially, when the lower NW is larger than the upper NW in stacked-NW FETs). Finally, in terms of the number of stacked NWs, the performance variation decreases as the number of stacked NWs increases, as long as the LER profiles of the NWs are poorly correlated.