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Novel Program Method of String Select Transistors for Layer Selection in Channel-Stacked NAND Flash Memory

机译:通道堆叠NAND闪存中用于层选择的串选择晶体管的新编程方法

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摘要

In this paper, we propose new string select transistors (SSTs)/dummy SSTs (DSSTs) threshold voltage (Vth) setting methods in simplified channel-stacked array with layer selection by multilevel operation (SLSM). In these methods, SSTs/DSSTs on each layer are set to their targeted Vth values by incremental step pulse program/one erase with various erase voltages, respectively. In the fabricated pseudo-SLSM, the validity of the new methods is verified. As a result, it is confirmed that the Vth values of SSTs/DSSTs are set to the targeted Vth values by the new methods and SSTs with extremely narrow Vth distribution can be obtained in the consequence. Moreover, memory operations such as erase, program, and read are performed in the fabricated structure after setting the Vth values of all the SSTs/DSSTs by the new methods. Despite unique LSM operations, stable memory operations are obtained successfully without the interference between stacked layers.
机译:在本文中,我们提出了一种新的字符串选择晶体管(SST)/虚拟SST(DSST)阈值电压(Vth)设置方法,该方法具有通过多级操作(SLSM)进行层选择的简化通道堆叠阵列。在这些方法中,通过递增步进脉冲编程/分别使用各种擦除电压进行一次擦除,将每一层上的SST / DSST设置为目标Vth值。在伪伪SLSM中,验证了新方法的有效性。结果,证实了通过新方法将SST / DSST的Vth值设置为目标Vth值,并且结果可以获得具有非常窄的Vth分布的SST。此外,在通过新方法设置所有SST / DSST的Vth值之后,在制造的结构中执行诸如擦除,编程和读取的存储操作。尽管有独特的LSM操作,但仍成功获得了稳定的内存操作,而没有堆叠层之间的干扰。

著录项

  • 来源
    《IEEE Transactions on Electron Devices》 |2016年第9期|3521-3526|共6页
  • 作者单位

    Inter-University Semiconductor Research Center, Department of Electrical Engineering and Computer Science, Seoul National University, Seoul, South Korea;

    Inter-University Semiconductor Research Center, Department of Electrical Engineering and Computer Science, Seoul National University, Seoul, South Korea;

    Inter-University Semiconductor Research Center, Department of Electrical Engineering and Computer Science, Seoul National University, Seoul, South Korea;

    Inter-University Semiconductor Research Center, Department of Electrical Engineering and Computer Science, Seoul National University, Seoul, South Korea;

    Inter-University Semiconductor Research Center, Department of Electrical Engineering and Computer Science, Seoul National University, Seoul, South Korea;

    Research and Development Division, SK Hynix Inc., Icheon, South Korea;

    Research and Development Division, SK Hynix Inc., Icheon, South Korea;

    Research and Development Division, SK Hynix Inc., Icheon, South Korea;

    Inter-University Semiconductor Research Center, Department of Electrical Engineering and Computer Science, Seoul National University, Seoul, South Korea;

    Inter-University Semiconductor Research Center, Department of Electrical Engineering and Computer Science, Seoul National University, Seoul, South Korea;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Decision support systems; Logic gates; Electric potential; Voltage measurement; Transistors; Computer architecture; Interference;

    机译:决策支持系统;逻辑门;电势;电压测量;晶体管;计算机体系结构;干扰;

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