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Comprehensive Analysis of Electrical Parameters Degradations for SiC Power MOSFETs Under Repetitive Short-Circuit Stress

机译:反复短路应力下SiC功率MOSFET的电参数劣化的综合分析

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摘要

The degradations of electrical parameters for silicon carbide power MOSFETs under repetitive short-circuit (SC) stress are investigated in detail in this paper. It demonstrates that the generation of negative charges along the gate–oxide interface of the channel region is the dominant degradation mechanism, which results in the increase in the threshold voltage (${V}_{ext {th}}$) and the rise of ON-state resistance (${R}_{ext {dson}}$) under low gate voltage bias condition. Furthermore, degradations of dynamic characteristics including gate charge (${Q}_{ext {g}}$) and switching behaviors of the device after the repetitive SC stress are extracted and analyzed for the first time. It illustrates that the increased${V}_{ext {th}}$contributes to the rise of the Miller plateau voltage (${V}_{ext {gp}}$), which further leads to the increase in gate–source charge (${Q}_{ext {gs}}$). Meanwhile, the increase in the turn-ON time and the reduction of turn-OFF time are observed, which are also resulted from the positive shifts of${V}_{ext {th}}$and${V}_{ext {gp}}$, leading to the rise of turn-ON switching energy (${E}_{{ ext {on}}}$) and the decline of turn-OFF switching energy (${E}_{ext {off}}$), respectively.
机译:本文详细研究了在重复短路(SC)应力下碳化硅功率MOSFET的电参数劣化。它表明,沿沟道区的栅极-氧化物界面产生负电荷是主要的降解机制,这导致阈值电压增加( n $ {V } _ { t​​ext {th}} $ n)和导通电阻的升高( n $ { R} _ { t​​ext {dson}} $ n)在低栅极电压偏置条件下。此外,包括栅极电荷在内的动态特性也会降低( n $ {Q} _ { t​​ext {g}} $ n)并首次提取并分析了重复SC应力后的器件开关行为。它说明了增加的 n <内联公式xmlns:mml = “ http://www.w3.org/1998/Math/MathML ” xmlns:xlink = “ http://www.w3.org/ 1999 / xlink “> $ {V} _ { t​​ext {th}} $ n促进了米勒平台电压( n $ {V} _ { t​​ext {gp}} $ n),这进一步导致门源电荷增加( n $ {Q} _ { t​​ext {gs}} $ n)。同时,观察到接通时间的增加和关断时间的减少,这也是由于 n <直列式xmlns:mml =“ http://www.w3”的正向偏移而引起的。 org / 1998 / Math / MathML “ xmlns:xlink = ” http://www.w3.org/1999/xlink “> $ {V} _ { text {th}} $ nand n $ {V} _ { t​​ext {gp}} $ n,导致接通开关能量的增加( n $ {E} _ {{ t​​ext {on} }} $ n)和关断开关能量的下降( n $ {E} _ { t​​ext {off}} $ n)。

著录项

  • 来源
    《Electron Devices, IEEE Transactions on》 |2018年第12期|5440-5447|共8页
  • 作者单位

    National ASIC System Engineering Research Center, Southeast University, Nanjing, China;

    National ASIC System Engineering Research Center, Southeast University, Nanjing, China;

    School of Electronic Science and Engineering, Southeast University, Nanjing, China;

    National ASIC System Engineering Research Center, Southeast University, Nanjing, China;

    National ASIC System Engineering Research Center, Southeast University, Nanjing, China;

    National ASIC System Engineering Research Center, Southeast University, Nanjing, China;

    National ASIC System Engineering Research Center, Southeast University, Nanjing, China;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Logic gates; Silicon carbide; Stress; MOSFET; Degradation; Voltage measurement; Stress measurement;

    机译:逻辑门;碳化硅;应力;MOSFET;性能下降;电压测量;应力测量;

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