机译:反复短路应力下SiC功率MOSFET的电参数劣化的综合分析
National ASIC System Engineering Research Center, Southeast University, Nanjing, China;
National ASIC System Engineering Research Center, Southeast University, Nanjing, China;
School of Electronic Science and Engineering, Southeast University, Nanjing, China;
National ASIC System Engineering Research Center, Southeast University, Nanjing, China;
National ASIC System Engineering Research Center, Southeast University, Nanjing, China;
National ASIC System Engineering Research Center, Southeast University, Nanjing, China;
National ASIC System Engineering Research Center, Southeast University, Nanjing, China;
Logic gates; Silicon carbide; Stress; MOSFET; Degradation; Voltage measurement; Stress measurement;
机译:基于Repetive短路应力下SiC功率MOSFET的低频噪声的陷阱分析
机译:基于重复动力循环应力下的低频噪声的SiC功率MOSFET的降解行为及缺陷分析
机译:短路应力对SiC功率MOSFET中SiO_2电介质降解的影响
机译:长期短路应力下SiC功率MOSFET的退化机理与优化研究
机译:电应力源对功率MOSFET降解过程影响的建模
机译:压力尿失禁尿道妇女盆腔地板电生理参数分析
机译:基于Repetive短路应力下SiC功率MOSFET的低频噪声的陷阱分析