Enhancement of PMOS device performance with poly-SiGe gate

摘要

Poly-Si and poly-Si/sub 0.75/Ge/sub 0.25/-gated PMOS transistors with a very thin gate oxide of 29 /spl Aring/ were fabricated. In addition to reduced gate-depletion effect (GDE) and reduced boron penetration, more favorable I/sub d/-V/sub d/ characteristics were observed for the poly-SiGe-gated transistors than poly-Si-gated transistors. This and the underlying superior hole mobility are explained with a universal mobility model based on V/sub g/, T/sub ox/, V/sub th/ and V/sub th/. Both reduced GDE and superior hole mobility contribute to the enhanced performance.