High-Efficiency Enhancement-Mode Power Heterojunction FET With Buried p{sup}+-GaAs Gate Structure for Low-Voltage-Operated Mobile Applications

摘要

This letter describes a successfully developed enhancement-mode double-doped AlGaAs/InGaAs/AlGaAs hetero-junction FET with a buried p{sup}+-n junction gate structure for low-voltage-operated mobile applications. The buried p{sup}+-GaAs gate structure effectively reduced on-resistance (R{sub}(on)) and suppressed drain-current frequency dispersion for the device with high positive threshold voltage, resulting in high-efficiency characteristics under low-voltage operation. The fabricated p{sup}+-gate HJFET exhibited a low R{sub}(on) of 1.4 Ω · mm with a threshold voltage of +0.4 V. Negligible frequency dispersion characteristics were obtained through pulsed current-voltage measurements for the device. Under a single 2.7-V operation, a 19.8-mm gate width device exhibited a power added efficiency of 51.9% with 26.8-dBm output power and a -40.1-dBc adjacent channel power ratio using a 1.95-GHz wideband code-division multiple-access signal.