Mechanisms Limiting EOT Scaling and Gate Leakage Currents of High- $k$/Metal Gate Stacks Directly on SiGe

摘要

This letter addresses mechanisms responsible for a high gate leakage current $(J_{g})$ and a thick interfacial layer in the surface channel SiGe pFET enabling transistor fabrication with sub-1-nm equivalent-oxide-thickness (EOT) high-$k$ /metal gate stack. The primary mechanism limiting EOT scaling is Ge-enhanced Si oxidation resulting in a thick (1.4-nm) $hbox{SiO}_{x}$ interface layer. A secondary mechanism, i.e., Ge diffusion ($geq$3%) into high- $k$, results in high $J_{g}$ . In the framework of this understanding, we optimized a high-$k$ nitridation process to form as an efficient diffusion barrier, which reduces both O and Ge diffusion resulting in the total gate stack EOT $sim$0.9 nm with $J_{g}$ comparable to that of bulk Si substrate samples. The proposed plasma nitridation process enables fabrication of the sub-1-nm EOT gate-first gate stack with HfSiON dielectric directly on SiGe without Si cap.