Investigation on the Retention Reliability of Scaled Inter-Poly Dielectrics for nand Flash Cell Arrays

摘要

We investigate the retention reliability of a 51-nm-node 16-GB nand Flash cell transistor comprising $hbox{SiO}_{2}/hbox{Al}_{x}hbox{O}_{y}/break hbox{SiO}_{2}$ inter-poly dielectric (OAO IPD). Despite the fact that OAO IPD retains low trapping rate being beneficial to retention reliability, the trap sites are located on shallow energy level, yielding a large amount of trap-assisted tunneling current at high temperature. Therefore, experimental results show two incompatible data retention characteristics of OAO IPD, namely, 33% worse $V_{rm TH}$ shift at 200 $^{circ}hbox{C}$ 2-h bake and 53% improved $V_{rm TH}$ shift after one week at 25 $^{circ}hbox{C}$, when compared to the case of ONO IPD.