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Self-Aligned Top-Gate Coplanar a-Si:H Thin-Film Transistors With a –Silicone Hybrid Gate Dielectric

机译:自对准顶栅共平面a-Si:H薄膜晶体管,带有-硅混合栅电介质

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We have made self-aligned top-gate coplanar hydrogenated amorphous-silicon (a-Si:H) thin-film transistors using a $hbox{SiO}_{2}$–silicone hybrid material as the gate dielectric. The hybrid dielectric layer is 150 nm thick and separates a chromium gate electrode from nickel silicide source and drain. The nickel silicide is formed by rapid thermal reaction of a deposited nickel film with the underlying a-Si:H. The electron field-effect mobility is $sim!! hbox{1.0} hbox{cm}^{2}/hbox{V} cdot hbox{s}$, the subthreshold slope is $sim$380 mV/decade, and the on/ off current ratio is $sim!! hbox{10}^{5}$. The gate leakage current of $sim$ 10 pA across the 150-nm-thick hybrid dielectric is $sim$1/10 of that observed across the typical 300-nm-thick $hbox{SiN}_{x}$ dielectric. The whole process needs only two masks.
机译:我们使用$ hbox {SiO} _ {2} $-有机硅杂化材料作为栅极电介质,制作了自对准顶栅共面氢化非晶硅(a-Si:H)薄膜晶体管。混合介电层的厚度为150 nm,并将铬栅电极与硅化镍的源极和漏极分开。通过沉积的镍膜与下面的a-Si:H的快速热反应形成硅化镍。电子场效应迁移率是$ sim !! hbox {1.0} hbox {cm} ^ {2} / hbox {V} cdot hbox {s} $,亚阈值斜率是$ sim $ 380 mV / decade,开/关电流比是$ sim! hbox {10} ^ {5} $。在150nm厚的混合电介质上的栅极泄漏电流为sim $ 10 pA,是在典型的300nm厚的$ hbox {SiN} _ {x} $介质中观察到的栅极泄漏电流为sim $ 1/10。整个过程只需要两个掩模。

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