Optimization of 40-nm Node Epitaxial Diode Array for Phase-Change Memory Application

摘要

A numerical model of an epitaxial (EPI) diode array for next-generation memory device application, including phase-change memory, has been presented. According to a diode array process scheme and technology computer-aided design (TCAD) simulation results, a quasi-physical model with a buried $ hbox{n}^{+}$ layer dosage, EPI layer thickness, and breakdown voltage (BVD) correlation is proposed to improve electrical performance. From the optimal silicon-based results, a 16 $ times$ 16 diode array shows a drive current density of $sim!! hbox{56.6} hbox{mA}/muhbox{m}^{2}$, a BVD of $sim$ 8 V, a $J_{rm on}/J_{rm off}$ ratio of $sim!!hbox{10}^{9}$, and crosstalk immunity. Additionally, this calibrated physical model can be applied in the next generation of silicon-based fabrication with parameters extraction.