Novel Select Gate Lateral Coupling Single Poly eNVM for an HVCMOS Process

摘要

We present a novel select gate (SG) lateral coupling embedded nonvolatile memory without any additional steps on a 90-nm high-voltage CMOS process. Usually, the SG coupling devices use a complex double poly process. However, continuing technology shrinkage makes the lateral coupling method possible for a single poly process. The SG of the novel cell is designed to function as a control gate and an SG at the same time, using only lateral capacitance coupling. Because of this distinct cell structure and operating principle, the memory cell has relatively small cell size, over-erase free, and multitime programmable features. The proposed cell is programmed by channel hot electron method and erased by band-to-band tunneling-assisted hot hole method, resulting in a 20-$mu{rm s}$ programming time and 100-ms erasing time. In addition, using this condition, we can achieve over 3 V threshold voltage $(V_{T})$ window over 500 cycles and an estimated over 10 year retention lifetime at 85$^{circ}$.