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High-Accuracy Deep Neural Networks Using a Contralateral-Gated Analog Synapse Composed of Ultrathin MoS₂ nFET and Nonvolatile Charge-Trap Memory

机译:高精度深度神经网络,采用对侧门控模拟突触组成的超薄MOS 2 NFET和非易失性充电陷阱记忆

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摘要

The development of high-accuracy analog synapse deep neural networks entails devising novel materials and innovative memory structures. We demonstrated an analog synapse with contralateral gates based on a two-dimensional (2D) field-effect transistor and nonvolatile charge-trapmemory. Vertical integration of a MoS2-channel FET with a charge-trapping layer provided excellent charge controllability and gate-tunable nonvolatile storage. In the proposed contralateral-gate design, the read andwrite operations were separated to mitigate read disturb degradation. Reducing the MoS(2)channel thickness to the ultrathin scale allowed large threshold voltage shifts and on-resistance (R-ON) modulations. This vertically integrated MoS(2)synapse device exhibited 55 conductance states, high conductance max-min ratio (G(MAX)/G(MIN); similar to 50), low nonlinearity of alpha(p) = -0.81 and alpha(d) = -0.31, near ideal asymmetry of 0.5, and free of read disturb degradation. High neural network accuracy (>87%) is also obtained.
机译:高精度模拟突触深神经网络的发展需要设计新颖的材料和创新的记忆结构。我们展示了基于二维(2D)场效应晶体管和非易失性电荷陷阱的对侧栅极的模拟突触。具有电荷捕获层的MOS2通道FET的垂直整合提供了出色的电荷可控性和栅极可调的非易失性存储。在建议的对侧门设计中,分离了读取的和写操作以减轻读干扰劣化。将MOS(2)的通道厚度降低到超薄秤允许大的阈值电压和导通电阻(R-ON)调制。该垂直集成的MOS(2)突触装置表现出55个电导状态,高导电MAX-MIN比(G(MAX)/ g(min);类似于50),低非线性α(P)= -0.81和α(D. )= -0.31,在理想的不对称附近0.5,无需读干扰劣化。还获得了高神经网络精度(> 87%)。

著录项

  • 来源
    《IEEE Electron Device Letters》 |2020年第11期|1649-1652|共4页
  • 作者单位

    Natl Chiao Tung Univ Dept Elect Engn Hsinchu 30010 Taiwan|Natl Chiao Tung Univ Inst Elect Hsinchu 30010 Taiwan;

    Taiwan Semicond Mfg Co Hsinchu 30075 Taiwan;

    Natl Chiao Tung Univ Dept Elect Engn Hsinchu 30010 Taiwan|Natl Chiao Tung Univ Inst Elect Hsinchu 30010 Taiwan;

    Natl Chiao Tung Univ Dept Electrophys Hsinchu 30010 Taiwan;

    Natl Chiao Tung Univ Dept Elect Engn Hsinchu 30010 Taiwan|Natl Chiao Tung Univ Inst Elect Hsinchu 30010 Taiwan;

    Natl Chiao Tung Univ Dept Elect Engn Hsinchu 30010 Taiwan|Natl Chiao Tung Univ Inst Elect Hsinchu 30010 Taiwan;

    Taiwan Semicond Mfg Co Hsinchu 30075 Taiwan;

    Natl Chiao Tung Univ Dept Electrophys Hsinchu 30010 Taiwan;

    Natl Chiao Tung Univ Dept Elect Engn Hsinchu 30010 Taiwan|Natl Chiao Tung Univ Inst Elect Hsinchu 30010 Taiwan;

    Natl Chiao Tung Univ Dept Elect Engn Hsinchu 30010 Taiwan|Natl Chiao Tung Univ Inst Elect Hsinchu 30010 Taiwan;

    Natl Chiao Tung Univ Dept Electrophys Hsinchu 30010 Taiwan;

    Taiwan Semicond Mfg Co Hsinchu 30075 Taiwan;

    Natl Chiao Tung Univ Dept Elect Engn Hsinchu 30010 Taiwan|Natl Chiao Tung Univ Inst Elect Hsinchu 30010 Taiwan;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Charge-trap memory; contralateral-gated; MoS2; neural networks; nonvolatile; transition metal dichalcogenide (TMD);

    机译:电荷陷阱记忆;对侧门控;MOS2;神经网络;非易失性;过渡金属二甲硅藻(TMD);

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