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Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide

机译:使用堆叠的高k型氧化物的无线双栅MOSFET分析亚阈值摆动

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In this paper, the subthreshold swing was observed when the stacked high-k gate oxide was used for a junctionless double gate (JLDG) MOSFET. For this purpose, a subthreshold swing model was presented using the series-type potential model derived from the Poisson equation. The results of the model presented in this paper were in good agreement with the two-dimensional numerical values and those from other papers. Using this model, the variation of the subthreshold swing for the channel length, silicon thickness, gate oxide thickness, and dielectric constant of the stacked high-k material was observed using the dielectric constant as a parameter. As a result, the subthreshold swing was reduced when the high-k materials were used as the stacked gate oxide film. In the case of the asymmetric structure, the subthreshold swing can be reduced than that of the symmetric JLDG MOSFET when the dielectric constant of the bottom stacked oxide film was greater than that of the top stacked oxide film. In the case of the asymmetric structure, the subthreshold swing could be also reduced by applying the bottom gate voltage lower than the top gate voltage.
机译:在本文中,当堆叠的高k栅极氧化物用于连接无线双栅极(JLDG)MOSFET时,观察到亚阈值摆动。为此目的,使用来自泊松方程的串联型电位模型来提出亚阈值摆动模型。本文呈现的模型的结果与来自其他论文的二维数值和其他纸张吻合良好。使用该模型,使用介电常数作为参数,观察到用于沟道长度,硅厚度,栅极氧化物厚度和堆叠的高k材料的介电常数和介电常数的亚阈值摆动的变化。结果,当高K材料用作堆叠的栅极氧化膜时,减少了亚阈值摆动。在非对称结​​构的情况下,当底部堆叠膜的介电常数大于顶部堆叠氧化物膜的介电常数时,亚阈值摆动可以减小。在不对称结构的情况下,通过施加低于顶栅电压的底部栅极电压也可以减少亚阈值摆动。

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