A dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination

摘要

A dual-output design of inverter chain that is hardened against P-hit single-event transient (SET) is proposed in this paper. The output nodes of the proposed inverter chain are hardened by dual-output topological structure design and stacked PMOSs with isolation. The simulation results based on a 65 nm CMOS technology suggest that the proposed design can eliminate SET pulse significantly. In comparison with the conventional inverter chain and inverter chain using the source-isolation technique, the proposed design is capable of maintain the output steadily irrespective of whether an ion hits “0” or hits “1”, i.e., the struck node is at logic “0” or logic “1”. Besides, the SET pulse occurring at any stage of inverter chains with the proposed methodology will not disturb the final output, as long as it does not occur at the final stage.