PULSE-REJECTING CIRCUIT FOR SUPPRESSING SINGLE-EVENT TRANSIENTS

摘要

A circuit for rejecting single-event transients (SETs) from logic signals is provided. The circuit includes a delay circuit (20), an inverter circuit (14), and an output-holding circuit (24). The delay circuit (20) receives an input signal (IN) and delays the input signal to produce a time-delayed version (IND) of the input signal. The input signal (IN) and the time-delayed version (IND) of the input signal are fed into the inverter circuit (14) that propagates a corresponding output signal (OUT) only when the input signal (IN) and the time-delayed version (IND) of the input signal have the same logic level. If the input signal (IN) or the time-delayed version (IND) of the input signal transitions such that both input signals presented to the inverter circuit (14) have opposite logic levels, the output-holding circuit (24) maintains the output signal in its previous state.