Pulse-rejecting circuit for suppressing single-event transients

摘要

A circuit for rejecting single-event transients (SETs) from logic signals is provided. The circuit includes a delay circuit, an inverter circuit, and an output-holding circuit. The delay circuit receives an input signal and delays the input signal to produce a time-delayed version of the input signal. The input signal and the time-delayed version of the input signal are fed into the inverter circuit that propagates a corresponding output signal only when the input signal and the time-delayed version of the input signal have the same logic level. If the input signal or the time-delayed version of the input signal transitions such that both input signals presented to the inverter circuit have opposite logic levels, the output-holding circuit maintains the output signal in its previous state.