This paper presents a method for decoding high minimal distance (dmin) short codes, termed Cortex codes. These codes are systematic block codes of rate 1/2 and can have higher dmin than turbo codes. Despite this characteristic, these codes have been impossible to decode with good performance because, to reach high dmin, several encoding stages are connected through interleavers. This generates a large number of hidden variables and increases the complexity of the scheduling and initialization. However, the structure of the encoder is well suited for analog decoding. A proof-of-concept Cortex decoder for the (8, 4, 4) Hamming code is implemented in subthreshold 0.25-μm CMOS. It outperforms an equivalent LDPC-like decoder by 1 dB at BER=10-5 and is 44 percent smaller and consumes 28 percent less energy per decoded bit.
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