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Performance Analysis of a Reconfigurable Shared Memory Multiprocessor System for Embedded Applications

机译:用于嵌入式应用的可重配置共享内存多处理器系统的性能分析

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摘要

This paper presents a method to predict performance of multiple processor cores in a reconfigurable system for embedded applications. A multiprocessor framework is developed with the capability of reconfigurable processors in a shared memory system optimized for stream-oriented data and signal processing applications. The framework features a discrete time Markov based stochastic tool, which is used to analyze memory contention in the shared memory architecture, and to predict the performance increase (speed of execution) when the number of processors is varied. Performance predictions for variations of other system parameters, such as different task allocations and the number of pipeline stages are possible as well. The results of the prediction tool were verified by experimental results of a green screen application developed and run on a Xilinx Virtex-II Pro FPGA with MicroBlaze soft processors.
机译:本文提出了一种在嵌入式应用的可重配置系统中预测多个处理器内核性能的方法。开发了一种多处理器框架,它具有在共享存储系统中可重新配置处理器的功能,该存储系统针对面向流的数据和信号处理应用进行了优化。该框架具有一个基于离散马尔可夫时间的随机工具,该工具可用于分析共享内存体系结构中的内存争用,并在处理器数量变化时预测性能提高(执行速度)。其他系统参数(例如,不同的任务分配和流水线阶段数)变化的性能预测也是可能的。预测工具的结果已通过在配备MicroBlaze软处理器的Xilinx Virtex-II Pro FPGA上开发并运行的绿屏应用程序的实验结果验证。

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