INVESTIGATION OF A LOW-COST HIGH-PERFORMANCE SHARED-MEMORY MULTIPROCESSOR SYSTEM FOR REAL-TIME APPLICATIONS

摘要

The proposed architecture can effectively support up to 64 modern digital signal processors (DSPs) in contrast to a smaller number of DSPs supported by existing bus-interconnected systems. This significant enhancement is achieved by introducing two small programmable fast memories (Twins) between the processor and the shared bus interconnect. While one memory is transferring data from/to the shared memory, the other is supplying the core processor with data. The elimination of the traditional direct linkage of the shared-bus and processor data bus makes feasible the utilization of a wider shared bus i.e., the shared bus width becomes independent of the data bus width of the processors. Simulation results show that the fast prefetching memories and the wider shared bus provide additional bus bandwidth to the system, which eliminates large memory latencies; such memory latencies constitute the major drawback for the performance of shared-memory multiprocessors with standard memory modules.