...
首页> 外文期刊>Innovative Systems Design and Engineering >Wallace Tree Multiplier Designs: A Performance Comparison Review
【24h】

Wallace Tree Multiplier Designs: A Performance Comparison Review

机译:华莱士树乘法器设计:性能比较回顾

获取原文
           

摘要

Multiplication process is often used in digital signal processing systems, microprocessors designs, communication systems, and other application specific integrated circuits. Multipliers are complex units and play an important role in deciding the overall area, speed and power consumption of digital designs. This paper presents a comparison review of various Wallace tree multiplier designs in terms of parameters like latency, complexity and power consumption. Keywords: Booth Recoding Algorithm, Carry Look Ahead Adder, Carry Select Adder, Compressors, Ripple Carry Adder, Sklansky Adder, Wallace Tree Multipliers.
机译:乘法过程通常用于数字信号处理系统,微处理器设计,通信系统和其他专用集成电路中。乘法器是复杂的单位,在决定数字设计的整体面积,速度和功耗方面起着重要作用。本文从延迟,复杂性和功耗等参数的角度对各种华莱士树乘法器设计进行了比较回顾。关键字:展位记录算法,进位超前加法器,进位选择加法器,压缩器,波纹进位加法器,Sklansky加法器,华莱士树乘法器。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号