A new circuit technique for reduced leakage current in Deep Submicron CMOS technologies

摘要

Modern CMOS processes in the Deep Submicron regime are restricted to supplyvoltages below 2 volts and further to account for the transistors' fieldstrength limitations and to reduce the power per logic gate. To maintain thehigh switching performance, the threshold voltage must be scaled accordingwith the supply voltage. However, this leads to an increased subthresholdcurrent of the transistors in standby mode (V_GS=0). Another source ofleakage is gate current, which becomes significant for gate oxides of 3nmand below. style="line-height: 20px;">We propose a Self-Biasing Virtual Rails(SBVR) - CMOS technique which acts like an adaptive local supply voltage incase of standby mode. Most important sources of leakage currents are reducedby this technique. Moreover, SBVR-CMOS is capable of conserving storedinformation in sleep mode, which is vital for memory circuits. style="line-height: 20px;">Memories are exposed to radiation causing soft errors. This well-knownproblem becomes even worse in standby mode of typical SRAMs, that have lowdriving performance to withstand alpha particle hits. In this paper, a16-transistor SRAM cell is proposed, which combines the advantage ofextremely low leakage currents with a very high soft error stability.