X-Tolerant Test Response Compaction

摘要

DIGITAL CIRCUIT TESTING involves applying test patterns and observing the circuit's responses to the applied patterns. The tester compares the observed response to a test pattern with the expected response and declares a chip defective upon mismatch. Test engineers usually obtain the expected response through fault-free simulation of the circuit for the corresponding test pattern. Unfortunately, fault-free simulation cannot always determine the expected response to be 0 or 1. In that case, the expected response is an unknown, or X. Of course, an actual defect-free or defective chip will produce 0 or 1; however, because the simulated expected response is X, we cannot compare the actual chip's response with a golden reference. Hence, this test response is ignored during testing. Table 1 explains testing in the presence of Xs. Table 2 summarizes the major sources of Xs in today's designs. Proper DFT techniques must be employed to minimize Xs. However, it is impractical to eliminate all X sources due to timing constraints, area overhead, simulation engine inefficiencies (such as 0-delay simulation), and inaccuracies in modeling the behaviors of certain memory, custom logic, and analog circuit blocks (also called black boxes). Some of these problems become visible very late in design or after IC manufacture, when it is difficult or impossible to insert additional DFT structures. Table 3 shows four industrial ASIC designs with their corresponding X densities--the percentage of response bits whose expected values are Xs.