Methods for using checksums in X-tolerant test response compaction in scan-based testing of integrated circuits

摘要

Methods for designing and using checksums in X-tolerant test response compaction in scan-based testing of integrated circuits. Flip-flops of a chip are treated as points of a discrete geometrical structure described in terms of points and lines (e.g., a two-dimensional structure, or the like). Each point represents a MUXed flip-flop holding a value. Each line (with points on it) represents a checksum: bit values of flip-flops corresponding to points on the line are all XORed together. A set of all checksums (“lines”) may be separated into subsets, where each subset contains parallel lines. One of these subsets (such that each point belongs to one of lines of the subset) represents scan chains, each line representing one scan chain. In a preferred embodiment, a compactor contains separate parts for each of these subsets such that complexity (the number of gates) of each part depends on the number of scan chains and does not depend on their lengths. Values of checksums may be used as follows. If a checksum includes at least one X-bit, the checksum is deleted from the set of calculated checksums. The remaining checksums of the set of calculated checksums are compared with pre-computed values. If the remaining checksums and the pre-computed values fail to match, then the chip is identified as malfunctional.