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Yield-Driven, False-Path-Aware Clock Skew Scheduling

机译:良率驱动的,错误路径感知的时钟偏斜调度

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SEMICONDUCTOR TECHNOLOGY ADVANCES have enabled designers to integrate more functionality in a single chip. As design complexity increases, many new design techniques are developed to optimize chip area and power consumption, as well as performance. Traditionally, yield improvement has been achieved through process improvement. However, in deep-submicron technologies, process variations are difficult to control. As a result, many design decisions significantly affect yield. Therefore, designers should consider yield-related issues during the design phase. Timing failure is a major cause of yield loss for highperformance circuits. Although designers have used clock skew scheduling to increase operation frequency, there is little research addressing its impact on yield. We propose a novel clock-skew-scheduling scheme that improves yield without sacrificing performance. The scheme achieves this by combining accurate path delay information using our efficient sensitizable-critical-path search algorithm and a proportional slack distribution heuristic. Our experimental results show substantial yield improvement in many of the ISCAS89 and ITC99 benchmark circuits, and in one case improvement is as high as 50percent.
机译:半导体技术的进步使设计人员能够在单个芯片中集成更多功能。随着设计复杂度的增加,开发了许多新的设计技术来优化芯片面积,功耗以及性能。传统上,通过工艺改进实现了产量的提高。然而,在深亚微米技术中,工艺变化难以控制。结果,许多设计决策都会显着影响良率。因此,设计人员应在设计阶段考虑与良率相关的问题。时序故障是高性能电路良率损失的主要原因。尽管设计人员已使用时钟偏斜调度来提高工作频率,但很少有研究解决其对良率的影响。我们提出了一种新颖的时钟偏移计划方案,该方案可以在不牺牲性能的情况下提高产量。该方案通过使用我们有效的敏感关键路径搜索算法和比例松弛分布启发式算法结合准确的路径延迟信息来实现此目的。我们的实验结果表明,许多ISCAS89和ITC99基准电路的良率都有实质性的提高,在一种情况下,提高幅度高达50%。

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