Yield-Driven, False-Path-Aware Clock Skew Scheduling

摘要

SEMICONDUCTOR TECHNOLOGY ADVANCES have enabled designers to integrate more functionality in a single chip. As design complexity increases, many new design techniques are developed to optimize chip area and power consumption, as well as performance. Traditionally, yield improvement has been achieved through process improvement. However, in deep-submicron technologies, process variations are difficult to control. As a result, many design decisions significantly affect yield. Therefore, designers should consider yield-related issues during the design phase. Timing failure is a major cause of yield loss for highperformance circuits. Although designers have used clock skew scheduling to increase operation frequency, there is little research addressing its impact on yield. We propose a novel clock-skew-scheduling scheme that improves yield without sacrificing performance. The scheme achieves this by combining accurate path delay information using our efficient sensitizable-critical-path search algorithm and a proportional slack distribution heuristic. Our experimental results show substantial yield improvement in many of the ISCAS89 and ITC99 benchmark circuits, and in one case improvement is as high as 50percent.